#### MaheshKS

##### Newbie level 3

Hiii all, am trying to do verilog coding for extended euclids algorithm.. i ve done the code but der is some problem in the code... it is not entering in to the else loop..(ie..if (B3!=1)).. plzzzz help me...

Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 module private_key( input rst,clk, input [7:0]e_in,n_in, output reg [7:0]d_out); reg [7:0]A1,A2,A3,B1,B2,B3,temp,temp1,temp2,temp3,quo,count,rem; always @(posedge clk) begin if(rst) begin A1<=1;A2<=0;A3<=n_in; B1<=0;B2<=1;B3<=e_in; end else begin if(B3) d_out<=B2; else begin temp <= A3; if (temp>=B3) begin temp<=temp-B3; count<= count+1; end else begin rem <= temp; quo <= count; end temp1<=A1; temp2<=A2; temp3<=A3; A1<=B1; A2<=B2; A3<=B3; B1<=temp1-(quo*B1); B2<=temp2-(quo*B2); B3<=temp3-(quo*B3); end end end endmodule

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